(1) Field of the Invention
The present invention relates to a semiconductor device improving a carrier mobility of a channel, thereby to realize a high-speed operation.
(2) Description of the Related Art
In a growing trend to finely fabricate an Si-based MOSFET, it is necessary to improve electrical characteristics such as a carrier mobility of a channel in order to realize a high-speed operation and low power consumption for a MOSFET. In Shinichi Takagi, “Metal-Oxide-Semiconductor (MOS) Device Technologies Using Si/SiGe Hetero-Interfaces”, Applied Physics, Vol. 72, No. 3 (2003) and J-S Lim et al., IEEE Electron Devices Letters, Vol. 25, No. 11 (2004), some candidates for a MOSFET channel structure are proposed. For example, as illustrated in FIG. 14, an SiGe layer 51 is used as a substrate. Herein, the SiGe layer 51 is formed above an Si crystal 50 and is subjected to lattice relaxation so as to have a lattice constant higher than that of the Si crystal 50. Then, a strained Si 52 is epitaxially grown on the SiGe substrate 51 and is used as a channel. In many cases, SiGe is subjected to lattice relaxation in such a manner that an inclined-type SiGe buffer layer 53 having a Ge concentration increased from 0% to a desired value is formed immediately below the SiGe layer 51. Further, as illustrated in FIG. 15, a buried insulating layer 55 may be formed between the inclined-type SiGe buffer layer 53 and the Si substrate. Alternatively, as illustrated in a left side of FIG. 23, a first-order internal stress film 60 is deposited immediately on a source region (S), a gate region (G) and a drain region (D) of an MOSFET (MISFET). Herein, the first-order internal stress film 60 is, for example, an SiN film that generates a tensile force. With this first-order internal stress film 60, Si in an Si channel region is restrained. Still alternatively, as illustrated in FIG. 16, an SiGe layer 151 is used as a channel. The former two methods are adopted for an nMOSFET and a pMOSFET, and the latter method is adopted for a pMOSFET. Among the aforementioned three methods, as strained Si, the former two methods are positively studied in recent years. Physically, strained Si is obtained because a band structure of Si is varied, degeneration of a band is released and an effective mass is changed. In terms of phenomenology, a linear combination of three components of a stress vector to be applied to a channel region with a constant called a piezoparameter expresses a change in carrier mobility of a channel with respect to an applied stress.
As for a MOSFET having a gate length of 100 nm, device simulation is carried out using a piezoparameter; thus, a relation between a stress and a change in mobility is obtained. FIGS. 17 to 19 show results of the relation as a graph, respectively. In each of FIGS. 17 to 19, a horizontal axis represents magnitude of each component of a stress which is applied to a channel region and is expressed in a unit of “MPa”, and a vertical axis represents a change amount of a mobility in a unit of “%”. In addition, a positive value of the stress represents a tensile stress, and a negative value thereof represents a compressive stress. In the respective graphs, black circle marks and a solid line represent results on an nMOSFET, and black triangle marks and a broken line represent results on a pMOSFET. FIGS. 17, 18 and 19 show a dependency on a stress Sx in a gate length direction (an X direction) on a (001) plane which is a main surface of an Si substrate, a dependency on a stress Sy in a direction perpendicular to the gate length direction (a Y direction), that is, a gate width direction on the (001) plane which is the main surface of the Si substrate and a dependency on a stress Sz in a direction perpendicular to the main surface of the Si substrate (a Z direction), respectively.
The following description is summarized from the results shown in FIGS. 17 to 19. When a stress in a direction shown by an arrow in FIG. 20 on the (001) plane which is the main surface of the Si substrate is applied to a channel region of a MOSFET, a carrier mobility is increased. In other words, an nMOSFET and a pMOSFET are different from each other in a direction of applying a stress.
As for an nMOSFET, when a tensile stress is applied to a channel region in a gate length direction extending from a source (S) toward a drain (D) (an X direction: a [110] direction in this case) on a main surface of an Si substrate, a mobility is increased. In contrast, a compressive stress is applied similarly, the mobility is decreased. As shown in FIG. 17, a change in mobility is increased almost linearly with respect to the tensile stress Sx to be applied. Likewise, when a tensile stress is applied to the channel region in a direction perpendicular to the gate length direction (a Y direction: a [−110] direction in this case) on the main surface of the Si substrate, the mobility is increased. In contrast, when a compressive stress is applied similarly, the mobility is decreased. Although not illustrated in FIG. 20, when a stress to be applied in a direction perpendicular to the main surface of the Si substrate (a Z direction) is applied in a compressive direction in addition to the stresses applied in the X and Y directions on the main surface of the Si substrate, the mobility is increased as shown in FIG. 19. In contrast, when such a stress is applied in a tensile direction, the mobility is decreased.
As for a pMOSFET, when a compressive stress is applied to a channel region in a gate length direction extending from a source (S) toward a drain (D) (an X direction: a [110] direction in this case) on a main surface of an Si substrate, a mobility is increased. In contrast, a tensile stress is applied similarly, the mobility is decreased. As shown in FIG. 17, a change in mobility is increased almost linearly with respect to the compressive stress Sx to be applied. Likewise, when a tensile stress is applied to the channel region in a direction perpendicular to the gate length direction (a Y direction: a [−110] direction in this case) on the main surface of the Si substrate, the mobility is increased. In contrast, when a compressive stress is applied similarly, the mobility is decreased. Although not illustrated in FIG. 20, when a stress to be applied in a direction perpendicular to the main surface of the Si substrate (a Z direction) is applied in a tensile direction in addition to the stresses applied in the X and Y directions on the main surface of the Si substrate, the mobility is increased as shown in FIG. 19. In contrast, when such a stress is applied in a compressive direction, the mobility is decreased. As for the pMOSFET, however, a change in mobility with respect to the stress applied in the Z direction (a vertical direction) is much smaller than that in the nMOSFET.
As described above, an nMOSFET and a pMOSFET are different from each other in a direction of applying a stress for increasing a mobility. In view of the aforementioned facts, conventionally, the following semiconductor devices have been proposed in order to increase a mobility of a MOSFET in a chip and to enhance current driving power.
JP09-321307A discloses a semiconductor device illustrated in FIG. 21. The semiconductor device includes an SiGe layer 72 serving as a strain applying semiconductor layer, a buried insulating layer 73 (an SiO2 layer in this case) and a strained Si layer 74 serving as a channel layer. Herein, the buried insulating layer 73 is formed so as to divide the SiGe layer 72 in a vertical direction. The strained Si layer 74 is formed on the SiGe layer 72. In addition, the buried insulating layer 73 is formed such that a thickness of the SiGe layer 72 becomes thin. Prior to formation of the strained Si layer 74, the SiGe layer 72 is subjected to heat treatment in order to reduce defects such as dislocation to be generated in the SiGe layer 72, upon formation of the SiGe layer 72 and the buried insulating layer 73.
JP2003-078116A discloses a semiconductor device illustrated in FIG. 22. The semiconductor device has a lamination structure that a first SiGe layer 114 is formed on a buried insulating layer 121 by a lamination method. Thereafter, a second SiGe layer 141 having a Ge concentration higher than that of the first SiGe layer 114 is formed on the first SiGe layer 114 and, then, an Si layer 142 is formed on the second SiGe layer 141. The Si layer 142 is turned into a strained Si layer by a difference in lattice constant from the second SiGe layer 141 serving as a base.
JP2005-005633A discloses a semiconductor device illustrated in FIG. 23. The semiconductor device includes a first-order internal stress film 60 and a second-order internal stress film 61. Herein, the first-order internal stress film 60 is formed on a source region and a drain region of an nMISFET and is made of a silicon nitride. The second-order internal stress film 61 is formed on a source region and a drain region of a pMISFET and is made of a TEOS. The first-order internal stress film 60 generates a tensile stress in an electron moving direction in a channel region of the nMISFET; thus, a mobility of an electron is enhanced. Moreover, the second-order internal stress film 61 generates a compressive stress in a hole moving direction in a channel region of the pMISFET; thus, a mobility of a hole is enhanced.
In a growing trend to finely fabricate an Si-based MOSFET, it is necessary to improve electrical characteristics such as a carrier mobility of a channel in order to realize a high-speed operation and low power consumption for a MOSFET. Therefore, as described above, in order to increase a carrier mobility of a channel, a structural devisal is made in a semiconductor chip manufacturing process so as to apply a suitable stress to a channel region. However, even when a stress generation structure in a semiconductor chip is optimized, deformation such as warpage derived from a thermal history in a package manufacturing process occurs at the semiconductor chip and a compressive stress due to the deformation is generated on an Si chip by a difference between laminated members in coefficient of thermal expansion, Young's modulus, or Poisson's ratio. Consequently, there arises a problem that an optimal stress generated in the semiconductor chip manufacturing process and spatial distribution thereof are deoptimized, so that a channel region cannot obtain magnitude of a desired stress and spatial distribution thereof.